History of chip packaging of electronic components

Packaging is the bridge between the inner world of the communication chip and the outer circuit. Imagine if the chip had no packaging, how would we use it? Chips would become so fragile that they might not be able to perform even the most basic circuit functions. So chip packaging is undoubtedly very important.

With the development of integrated circuit, there are dozens of kinds of packaging, not all of us use, from the structure can be seen, the development of packaging :TO->DIP->SOP->QFP->PLCC->BGA->CSP.

The first category: the TO (Transisitoroutline)

The earliest type of packaging, TO, stood for transistor case, and many transistors are still visible today.

This TYPE of SOT also comes in the form of a transistor patch, and SOT-23 is the common triode package form.

The second category: DIP (DoubleIn - linePackage)

DIP, or dual-in-line package, is the first type of package in which we learn about electronic contact.

Why was DIP the first package we touched? When we first learned about electronic products, everyone would use bread board, learning 51 microcontrollers, this kind of packaging is often used. This kind of packing chip has large area, convenient welding, suitable for zero-base small white.

History of chip packaging of electronic components

However, although DIP packaging is easy to use, it has drawbacks. The chips in this package are easily damaged during insertion and removal. In addition, reliability is relatively poor. It is not suitable for making high-speed circuits. As a result, DIP packaging was gradually replaced with the development of integrated circuits.

Third class: SOP (SmalloutlinePackage)

If DIP is the most common in-line packaging, SOP is the most common patch packaging and is found everywhere in various integrated circuits. SOP, namely small appearance packaging, basically using plastic packaging. The pins are l-shaped from both sides of the package.

In 1968~1969, Phillips successfully developed THE SOP packaging technology, which was gradually derived:

SOJ, J pin small profile package.

TSOP, thin package.

VSOP, the external package is small.

SSOP, reduced SOP.

TSSOP, a thin, narrow SOP.

SOT, small transistor.

SOIC, small form factor integrated circuit.

Advantages of SOP packaging: there are many pins around the packaging chip, packaging operation is convenient, high reliability, is one of the mainstream packaging methods.

Class 4: QFP (QuadFlatPackage)

QFP, that is, small square flat packaging. QFP packaging has pins around the particles and identification is quite obvious. Flat packing with four side pins. One of the surface mount packages, the pins lead out the seagull wings (L) from the four sides.

TQFP package, PQFP package, TSOP package are developed on the basis of QFP.

TQFP is the abbreviation of ThinQuadFlatPackage, that is, thin plastic sealed quad-angle flat package. Four-sided flat package technology can effectively use the space, reduce the printed circuit board space size requirements.

PQFP is the abbreviation of PlasticQuadFlatPackage. PQFP packs chips with small distances between pins and thin pins. Generally large scale or very large scale integrated circuits use this form of packaging, pin number is generally more than 100.

TSOP is short for thin Outlinepackage, a thin and small package. A typical feature of TSOP memory packaging technology is pins around the packaging chip. TSOP is suitable for SMT (surface mount) technology to install wiring on PCB. TSOP packaging appearance, parasitic parameters (when the current changes significantly, will lead to output voltage disturbance) reduced, suitable for high-frequency applications, easy to operate, high reliability.

Class 5: PLCC (PlasticLeadechipCarier)

PLCC, that is, plastic package J wire chip package. PLCC package, square shape, 32-foot package, surrounded by pins, shape size is much smaller than DIP package. PLCC packaging is suitable for SMT surface mounting technology to install wiring on PCB, with the advantages of small shape, high reliability.

Compared to the QFP package described above, the pin is in the hook and is not deformable, but is more difficult to remove than the QFP package.

Class 6: BGA (BallGridArarayPackage)

Chip integration has been increasing, the number of I/O pins has also increased sharply, power consumption has also increased, and the requirements for integrated circuit packaging are more stringent. In order to meet the needs of development, BGA packaging began to be applied.

BGA, or ball grid array packaging. Compared with TSOP, BGA has smaller volume, better heat dissipation and better electrical performance. BGA packaging technology greatly improves storage capacity per square inch. In the same capacity, the memory product volume of BGA packaging technology is only one third of TSOP packaging. In addition, compared with the traditional TSOP packaging method, BGA packaging method has a faster and more effective cooling mode. However, when it comes to welding, BGA is many times more difficult than ordinary people can weld.

Class 7: CSP encapsulation.

In all kinds of packaging, CSP is the smallest area, the smallest thickness of the packaging, so it is the smallest volume of packaging. The number of input/output ends of CSP can be made much more in various packages of the same size. This kind of packaging is often found in the packaging of memory chips.

Packaging type is an important consideration in PCB selection and design schematics. Incorrect packaging drawing, incorrect chip welding, cost increase, waste of time. Therefore, I remind you to double check the packaging of the chip.

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