Intel next-generation process details exposed: 200 million transistors per square millimeter?

As you know, Intel's old roadmap had 14nm, 10nm, and 7nm processes, with 7nm being the first EUV-based process and twice as dense as 10nm. Intel eventually updated their roadmap to bring it more in line with the numbering schemes used by Samsung and TSMC.

Intel has several versions of the 10nm process, the original version (or both), then the Super Fin and Enhanced Super Fin versions. Under the new scheme, Intel's 10nm enhancedsuper fin version becomes Intel 7, while the previous 7nm process is replaced by Intel 4.

Intel's 10nm transistors have a density of about 100 million transistors per square millimeter, which is in line with Samsung's and TSMC's 7nm processes. I also believe that the performance of Intel's Enhanced Super Fin process is as good as any of the foundry 7nm processes. Therefore, renaming Intel's 10nm Enhanced Super Fin to Intel 7 is a more appropriate name for the number of foundamers.

When Intel announced Intel 4, they said it would offer a 20% performance per watt improvement and significant density improvements, but they didn't provide specific numbers. I think this probably means they're giving up on pursuing the 2x density improvement they've been pursuing before, but the tip sheet shows it's still 2x relative to 7nm. This puts the density somewhere between TSMC's 5nm and 3nm processes, so Intel 4 is once again the name consistent with the foundry naming convention.

Intel next-generation process details exposed: 200 million transistors per square millimeter?

Does that mean Intel 4 will have about 200 million transistors per square millimeter? This is actually a less straightforward question than you might think. When companies disclose the dimensions of their processes, they typically disclose values that are less than those in standard cells. For example, TSMC says their 7nm process has 54nm contact poly pitch (CPP), but our strategic partner TechInsights has measured 57nm in the standard cell in the actual design. What we have standardized when describing a process is the use of the densest standard units seen on the actual part (once the part is available for analysis). TechInsights first saw Intel's 10nm component, which it calls the first generation, in 2018.

The first generation of 54nm CPP is in line with Intel's claims. TechInsights saw a second-generation component in 2019 that also had 54nm CPP (the fin was higher than the first-generation, indicating a new generation). When Intel introduced the 10nm Super Fin version, they added an optional 60nm CPP for the high-performance unit. TechInsights analyzed these components (generation 3) and looked at 54nm and 60nm CPP units. Based on our convention, this still works out to about 100 million transistors per square millimeter.

Intel next-generation process details exposed: 200 million transistors per square millimeter?

Interestingly, TechInsights recently conducted an analysis of the Enhanced Super Fin process (10nm 4th generation, now called Intel 7). The process also has an optional 60nm CPP, but interestingly, in standard unit logic, TechInsights only sees 60nm CPP, not 54nm CPP and higher orbital heights. This resulted in a calculated density of about 60 million transistors per square millimeter. So is the Intel 4 200 million transistors per square millimeter (100 x 2) or 120 million transistors per square millimeter (60 x 2)? It's worth watching

My belief is that there will be 200 million transistors per square millimeter, but it will be interesting to see how many of the actual designs take advantage of this density.

There is more data in the tip table to help answer this question. Leading-edge process chips have a public CPP of 50nm and a minimum metal spacing of 30nm. Current leading-edge processes use a single diffusion interrupt, so we will assume that here as well. The only problem left is the orbit height, if I assume that each unit has 1 fin-5 orbit unit, then the density is about 200 million transistors per square millimeter. Individual fin units may require aggressive performance enhancements to meet Intel's performance requirements, and there may be other design-technical-collaborative optimizations along the way. For FinFET without an embedded power rail, a 5-rail unit is possible, so this could be a solution.

It will be interesting to see what other data is included in the whole paper. The fact that Intel is offering this paper does add extra weight to Intel's hopes of launching the Intel 4 later this year.

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