Yesterday we learned what CP test of chips is, as well as related test content and methods, so today we strike while the iron is hot, to understand the process of CP test.
1, with a self-testing program chip
First of all, there are some special chips to be distinguished separately. That is, the memory chips of self-designed and self-tested programs we talked about yesterday. These chips have prepared TestPlan at the beginning of design, and the test content and test method have been planned according to the specifications of their chips.
Chips typically have several TestMode functions ready to perform each type of test by configuring pins to put the chip into a specified test state. Such as:
ATPG can output WGL or STIL files for use by Tester.
BIST (Built-in SelfTest) logic. These self-test logic perform tests on ROM/RAM/Flash and other functions.
The Function Test Mode. Some specialized functional tests require additional hardware logic, such as ADC/DAC/ clock, etc.
For more information, please check out an updated article from Goodwill Semiconductor, which provides details.
2. Select test plant and test model
First of all, we need to choose a test plant with strength and a matching test model. The selection of test plant and test machine should consider chip type, test content, test specifications and cost and other factors.
According to the types of chips and test contents, the test machine can be divided into many series: for example, Advantest T55xx series of memory chips, Teradyne J750 series of digital mixed signal or SoC chips, Credence ASL-3000 series of RF chips.
3. Make ProbeCard and Test Program
After selecting the Test machine, the next step is to make ProbeCard and Test Program.
ProbeCard includes probes and chip peripheral circuits. At the time of chip design, the coordinates and arduous information of each DIE and each chip pin on the DIE have been determined before production. According to these parameters, probes can be made. It takes a lot of time to measure chips one by one. Therefore, the probe card can also choose Site to measure multiple chips at the same time, reducing the number of testing machines and saving time and cost. However, due to the limitation of testing machine resources, the number of simultaneous measurement is also limited, such as 32/16/8/4.
Probe materials also have different choices, such as tungsten copper, beryllium copper or palladium materials, these probes have their own characteristics in strength, conductivity, life, cost and other aspects, according to the needs of the choice.
A Test Program is a Test Program. The test program controls the whole machine test process. Different testing machines have different testing software systems, corresponding testing programs also have different formats. Usually engineers provide WGL/STIL/VCD files, and then convert them to the file format required by the test machine, and add other test programs.
4. Debugging and result analysis
During debugging, according to TestPlan, Pattern (test vector) is divided into different BIN, so as to locate test errors. During debugging, an incorrect Cycle position in Pattern can be directly seen on the system. Engineers debug according to the error information, modify the Pattern and test programs, and clean them one by one until all bins pass. The same test Site debugging through all, so the cycle after several rounds, you can start the trial run.
At this time, the engineer also needs to debug the probe strength, cleaning the probe cycle and other parameters to ensure that every Touchdown on the whole Wafer can be tested and stabilized.
Finally, the test results of the entire Wafer will generate a Wafer diagram file, and the data will generate a log file, such as STD file. The wafer graph mainly contains yield, test time, error number of each BIN and DIE position, and the log file is the specific test results. Engineers analyze the data to decide whether to go into mass production.
5. Debug again and optimize the process
Finally, it was time to move into mass production, where some adjustments could be made to further optimize the testing process based on statistics from a large number of tests.
At this stage, it is possible to decide whether to retest the DIE that failed or not. Normally, retest can correct a certain proportion of errors, but requires more testing time. Therefore, it is necessary to decide whether to retest after comprehensive consideration. Generally, the DIE at the Wafer edge has a high probability of error. Considering comprehensively, sometimes the edge DIE can be directly removed and marked as bad without testing, so as to save test time.
In addition, we also need to pay attention to whether the yield rate is stable. When the yield rate is continuously low, we need to stop the test, conduct data analysis, check the equipment or communicate with the OEM.
The next step is to enter the real mass production, at this time only need to submit the RESULT of CP test to the subsequent sealing factory. It is usually a Map file containing BIN information. According to the Map file, the packaging factory selects good products and encapsulates them, removes bad products, and retains the special BIN selected by customers.